.command -ai ; output in Intel hex format
;
; Listing 1.  Test program for Scroungemaster II.
; Can be run from a 2764, 27128, or 27256 EPROM.

        ; 6809 reset vector
        .org h'fffe
        .dw  entry

        ; program addresses of on-board I/O,
        ;   when 7xxx is mapped to FFxxx.
        .equ endram,h'7c00
        .equ sccbcmd,h'7c00
        .equ sccbdta,h'7c01
        .equ sccacmd,h'7c02
        .equ sccadta,h'7c03
        .equ sccdcmd,h'7c80
        .equ sccddta,h'7c81
        .equ sccccmd,h'7c82
        .equ scccdta,h'7c83
        .equ pio,h'7d00
        .equ led,h'7d80
        .equ io4,h'7e00
        .equ io5,h'7e80
        .equ io6,h'7f00
        .equ io7,h'7f80

; Scroungemaster II minimal initialization.
; When the SM II is powered up, the mapping RAM
; is in an unknown state, so only the EPROM and
; mapping RAM can be accessed.  The first thing
; we must do is put the mapping RAM in a known
; state.  This mapping will make the on-board I/O
; accessible.  No matter what RAM chip is
; installed, 7K of RAM will be available from
; program addresses E000 to 7BFF.  Remember that
; the mapping values are logically inverted by
; the mapping RAM.
        .org h'fe00
entry:  clra
        sta  h'f000     ; map 7xxx -> FFxxx
        inca            ;   (on-board RAM & I/O)
        sta  h'e000     ; map 6xxx -> FExxx
        inca            ;   (on-board RAM)
        sta  h'd000     ; map 5xxx -> FDxxx
        inca
        sta  h'c000     ; map 4xxx -> FCxxx
        inca
        sta  h'b000     ; map 3xxx -> FBxxx
        inca
        sta  h'a000     ; map 2xxx -> FAxxx
        inca
        sta  h'9000     ; map 1xxx -> F9xxx
        inca
        sta  h'8000     ; map 0xxx -> F8xxx

        ; A simple loop to output 00->FF to LEDs,
        ; without using any RAM.  Remember that
        ; the LEDs will appear logically inverted
        ; ("1" = off, "0" = on).
        clrb
tloop:  leax 1,x        ; increment counter lo 16
        bne tloop
        incb            ; increment counter hi 8
        stb led         ; output to LEDs
        bne tloop

        ; Initialize one Zilog SCC.  Subroutines
        ; require the use of the stack, so this
        ; needs RAM.  Also note that some common
        ; SCC registers are set up in the port A
        ; table, and some in the port B table, so
        ; you need to initialize BOTH ports.
        lds #endram     ; point stack to RAM top
        ldx #sccatbl    ; port A setup table
        jsr sccinit     ; common init routine
        ldx #sccbtbl    ; port B setup table
        jsr sccinit     ; common init routine

        ; A simple loop to receive a character,
        ; output it to the LEDs, increment it,
        ; and output it to the serial port.  We
        ; know that by the time one character is
        ; received, the transmitter will be ready
        ; to send one character.
qloop:  ldb sccacmd     ; wait for rx char avail.
        andb #1
        beq qloop
        ldb sccadta     ; input char from scc
        stb led         ; output char to led
        incb
        stb sccadta     ; output char+1 to scc
        bra qloop

        ; Zilog SCC initialization routine,
        ; entered with table address in X.
        ; You can use this routine in your own
        ; applications.
sccinit: ldy ,x++   ; get scc port address
         ldb ,x+    ; get # of bytes to output
sccloop: lda ,x+    ; get byte from table
         sta ,y     ; store to SCC port
         decb
         bne sccloop
         rts

sccatbl: .dw sccacmd    ; port address
 .db 37          ; 37 bytes follow
 .db h'0         ; just in case, reset reg ptr
 .db h'9,h'0c0   ; hardware reset, irpts off
 .db h'4,h'44    ; 16x clock,async,1 stop,no par.
 .db h'1,h'0     ; no dma, all irpts disabled
 .db h'2,h'0     ; irpt vector (for future use)
 .db h'3,h'0c0   ; rx 8 bits, rx disabled
 .db h'5,h'60    ; tx 8 bits, tx disabld, RTSA hi
 .db h'9,h'1     ; status low, irpts off
 .db h'0a,h'0    ; nrz encoding
 .db h'0b,h'50   ; no xtal, BRG->rxc txc, TRxC in
 .db h'0c,h'18   ; BRG lo byte - 4800 baud at 16x
 .db h'0d,h'0    ;     hi byte - w/ 4 MHz BRG clk
 .db h'0e,h'2    ; DTR pgm'd, BRG from PCLK
 .db h'0e,h'3    ; as above, plus BRG enabled
 .db h'3,h'0c1   ; as above, plus rx enabled
 .db h'5,h'68    ; as above, plus tx enabled
 .db h'0f,h'0    ; no ext/sts interrupts
 .db h'10,h'10   ; reset ext/sts interrupts twice
 .db h'1,h'0     ; no dma, all irpts disabled

sccbtbl: .dw sccbcmd    ; port address
 .db 31          ; 31 bytes follow
 .db h'0         ; just in case, reset reg ptr
 .db h'4,h'44    ; 16x clock,async,1 stop,no par.
 .db h'1,h'0     ; no dma, all irpts disabled
 .db h'3,h'0c0   ; rx 8 bits, rx disabled
 .db h'5,h'60    ; tx 8 bits, tx disabld, RTSB hi
 .db h'0a,h'0    ; nrz encoding
 .db h'0b,h'50   ; no xtal, BRG->rxc txc, TRxC in
 .db h'0c,h'18   ; BRG lo byte - 4800 baud at 16x
 .db h'0d,h'0    ;     hi byte - w/ 4 MHz BRG clk
 .db h'0e,h'2    ; DTR pgm'd, BRG from PCLK
 .db h'0e,h'3    ; as above, plus BRG enabled
 .db h'3,h'0c1   ; as above, plus rx enabled
 .db h'5,h'68    ; as above, plus tx enabled
 .db h'0f,h'0    ; no ext/sts interrupts
 .db h'10,h'10   ; reset ext/sts interrupts twice
 .db h'1,h'0     ; no dma, all irpts disabled
; .db h'9,h'9  ; as above,plus irpt master enable

        .end